Cadence Virtuoso Online Training by Techpratham teaches students how to design, simulate, and verify custom ICs. Using Virtuoso tools, this course gives you hands-on experience with schematic entry, layout design, and post-layout verification.
Level
Advanced
Duration
8 weeks



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Rated #1 Recognized as the No.1 Institute for Cadence Virtuoso Online Training Course. We know a lot about designing, laying out, and simulating custom ICs. The training includes schematic-driven design, layout of both analog and digital circuits, parasitic extraction, and checking performance. Using advanced Cadence tools, students get to design circuits in the real world. This class is perfect for semiconductor professionals, VLSI engineers, and analog designers.
Working professional who is carrying more then 10 years of industry experience.
Access to updated presentation decks shared during live training sessions.
E-book provided by TechPratham. All rights reserved.
Module-wise assignments and MCQs provided for practice.
Daily Session would be recorded and shared to the candidate.
Live projects will be provided for hands-on practice.
Expert-guided resume building with industry-focused content support.
Comprehensive interview preparation with real-time scenario practice.
Overview of Virtuoso platform and analog/mixed-signal design flow.
Understanding Virtuoso environment and library management.
Creating and managing analog schematics in Virtuoso.
Running and analyzing circuit simulations.
Design of basic analog building blocks.
Physical layout creation using Virtuoso Layout Editor.
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Schematic and Layout of CMOS Inverter
Use the Virtuoso schematic editor to design a CMOS inverter, test how it works, and make the layout that goes with it. Use LVS and DRC checks to make sure the design is correct.
Operational Amplifier Design & Verification
Make a full op-amp schematic, test the frequency response, and build the layout. Do parasitic extraction and check that the design is correct.
Mixed-Signal Circuit Design
Make a mixed-signal block (ADC or DAC), do schematic-driven layout, and then run post-layout simulations with parasitics. Make sure it works well and is reliable.

Why is Cadence Virtuoso important for VLSI engineers?

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